Does anyone know exactly how to put vias on MLF ground pads and keep eagle from flagging them as overlap/clearance DRC violations? I know I can "approve" the errors, but I was just wondering if there was another way.

Also, is there a way to make the pads round on one end and square on the other end like some MLF pad landings suggest? I know it isn't mandatory to have rounded ends, it would just be nice.

I am not sure about Eagle but in Altium you can configure the pad shape and size within the PCB library part editor. As for the vias in pad, there should be some kind of rules file (or menu) in Eagle which will allow you to 'allow' this kind of thing.
Altium will allow vias in pad by default and I suspect that Eagle will do the same - can you verify that the vias you are placing in the pads are connected to the same net as the pad? ie. If you place a via associated with one net in a pad associated with another this would flag a violation (and rightfully so).
In the meantime I will try to find an answer for you - its better to do these things properly rather than ignore (or approve) errors without knowing why they have been flagged!

S.

YZF600 - would it be possible to add some info to the 'introducing..' section in the forum?
I have made a start with my own 'about me' thing but it would be good to get some background on you guys too!

Thanks,

S.

Another question on the Eagle...
What would be the most simple way to implement jumper cables in board design? I don't want to make 100 different components w different lengths, I would like a way to position two solder points where I would later solder the jumper, and that should be it!

Hi mrMister,

When you mention 'jumper links' do you mean a wire link on a single-sided PCB (ie. Substrate only has copper on one side of the board) jumping over pre-routed PCB traces?
If so, you could place through-hole testpoint symbols within the net (within the schematic) and just show a graphical connection between them (on the schematic) for clarity and 'understandability' on the schematic. This would mean that when it comes to routing the PCB you would effectively have two different nets with a through-hole testpoint on each which can be linked with a bit of wire
I know what I mean but I am not sure what you are after - if you can clarify (preferably with a picture!) then I am sure I can advise

S

I always do this:
1) make vias bigger so they are usable for a wire bridge
2) route (almost) all traces on the bottom (solder) layer
3) if you need a wire bridge route it on top (component) layer
4) dont print/gerber to top layer copper
5) if you use the top layer silkscreen for production of the pcb or documentation:
add traces top to it so you get a line where you need to solder the wire